ATHENA SENSOR ARITHMETIC PROCESSOR (ASAP)

FUTURE MILITARY SYSTEMS WILL HAVE AN INCREASING NEED TO ACHIEVE A HIGHER AND MORE COMPLETE LEVEL OF SENSOR FUSION THAN CURRENTLY EXISTS. THE RATIONALE FOR SSNSOR FUSION IS GENERALLY WELL ACCEPTED AND RELATES TO PERFORMANCE, RELIABILITY, MODULARITY, AND EXTENSIBILITY. IT IS NOW DESIRED TO INTEGRATE DIGITAL PROCESSORS WITH SENSOR ARRAYS TO FORM SMART SENSOR GROUPS. THE PROPOSED TECHNOLOGY, THE ATHENA SENSOR ARITHMETIC PROCESSOR, OR ASAP, WILL ATTEND NOT ONLY TO RF AND OPTICAL SENSOR FUSION IMPLEMENTATION ISSUES, BUT WILL ALSO BE ABLE TO RESPOND TO THE HIGHER ORDER PROBLEM OF SYSTEM INTEGRATION. TO ACHIEVE THE HIGH-BANDWIDTH, ULTRA-COMPACT CHANNELIZER, WE WILL INTEGRATE OUR PROVEN DSP FILTERING CAPABILITIES WITH THE UNPARALLELED ADVANTAGES OF OUR ARITHMETIC PROCESSOR, WHICH IS BASED ON THE RESIDUE NUMBER SYSTEM (RNS). MORE SPECIFICALLY, WE WILL INTEGRATE AN RNS TECHNOLOGY WHICH WE BELIEVE IS THE MOST ADVANCED IN THE INDUSTRY, AN RNS SYSTEM INTEGRATION AND VLSI EXPERIENCE, AND PROVEN DSP CAPABILITIES. THE NEW RESEARCH THRUST WILL LEAD TO RNS BASED ARCHITECTURES AND SYSTEMS CAPABLE OF WORKING FROM 100MHZ (CMOS) TO 1GHZ (GAAS). THE DEVELOPED ASAP TECHNOLOGY WILL BE EXPECTED TO HAVE AT LEAST A 100-FOLD SPEED-AREA RATIO IMPROVEMENT OVER CONVENTIONAL TECHNOLOGIES. WE WILL DEMONSTRATE, USING SIMULATION AND ANALYSIS, OUR ABILITY TO SUPPORT HIGH-BANDWIDTH SENSOR SIGNAL PROCESSING AS WELL AS DEVELOP ITS VLSI SPECIFICATION. THE RESEARCH ALSO DEVELOPS ASAP AS A FAULT-TOLERANT SENSOR SIGNAL PROCESSOR.