THE REDUCED INSTRUCTION SET COMPUTER BASED PROCESSOR MODULE FOR FASTBUS COMPUTATION APPLICATIONS

THE FASTBUS SYSTEM SPECIFICATION FOR HIGH ENERGY PHYSICS ANDOTHER DATA-SYSTEM APPLICATIONS ANTICIPATES THE USE OF MULTIPLE, HIGH PERFORMANCE PROCESSOR MODULES FOR DATA CONTROL AND EVENT REDUCTION ASSOCIATED WITH EXPERIMENTS IN THE PHYSICAL SCIENCES. EXISTING PROCESSOR DESIGNS WILL BE UNABLE TO COPE WITH THE PROJECTED DATA-REDUCTION AND EVENT-HANDLING REQUIREMENTS OF THE COMPLEX EXPERIMENTS PLANNED FOR THE NEXT GENERATION OF PARTICLE ACCELERATORS. A HIGH PERFORMANCE FASTBUS PROCESSOR MODULE USING THE REDUCED INSTRUCTION SET COMPUTER (RISC) INTEGRATED-CIRCUIT TECHNOLOGY, COUPLED WITH A SINGLE ASIC MASTER INTERFACE TO THE FASTBUS SEGMENT, WILL BE DEVELOPED IN THIS PROJECT. THE PLANNED PERFORMANCE GROWTH OF THE RISC PROCESSOR FAMILIES MATCHES THE PROJECTED REAL-TIME PROCESSING NEEDS OF THE PROPOSED NEW EXPERIMENTS; AN EFFICIENTLY COUPLED ASIC MASTER INTERFACE WILL ALLOW THE RISC PROCESSOR TO TAKE FULL ADVANTAGE OF THE BANDWIDTH OF THE FASTBUS DATA PATHS. DURING THE PHASE I RESEARCH A FEASIBLE RISC PROCESSOR FAMILYWILL BE SELECTED THAT HAS A PLANNED GROWTH IN PERFORMANCE TO AT LEAST 100 MILLION INSTRUCTIONS PER SECOND. THE GENERAL ARCHITECTURE OF THE PROCESSOR MODULE WILL BE DEVELOPED SO THAT IT IS CAPABLE OF EFFECTIVELY USING A RISC DEVICE. THE MASTER INTERFACE ASIC TO CONNECT THIS HIGH PERFORMANCE PROCESSOR ELEMENT TO FASTBUS WILL BE DEFINED IN ORDER TO ENSURE THAT A COMMERCIAL SOFTWARE PLATFORM WILL BE AVAILABLE FOR EFFICIENT TARGET CODE DEVELOPMENT.