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Award details
- Awarding agency
- Department of Defense
- Branch
- Navy
- Recipient company
- INTELLISENSE SYSTEMS INC
- Proposal award date
- 2025-06-17
- Contract end date
- 2025-12-14
- UEI
- C4Y5CNN55L37
- Solicitation number
- 25.1
- Topic code
- N251-042
Research abstract
To address the Navyís need for a comprehensive, multi-layered approach to address computing infrastructure resilience (CIR) and enhance the overall reliability and efficiency of edge computing chiplet-based environments, Intellisense Systems, Inc. (Intellisense) proposes to develop a new Zero-Trust Technology for Advanced Chiplets (Z-TAC) based on a multi-layered security approach that integrates hardware-based authentication (attestation of both data and sources) using UCIe packet structures with software-defined zero-trust networking. Specifically, the innovation in Z-TAC lies in its unique combination of hardware-embedded security within UCIe interconnects and dynamic, software-defined access control through a zero-trust framework. Unlike traditional security models that rely on perimeter-based defenses, Z-TAC ensures continuous authentication and least-privilege access control at both the chiplet and network levels, software and hardware components are only granted access to the minimal resources required to complete their work. This enables Z-TAC to detect and mitigate unauthorized access attempts in real time, ensuring that only verified components and users can interact within the system. As a result, Z-TAC will enhance computing infrastructure resilience by providing robust protection against supply chain vulnerabilities, cyber intrusions, and insider threats. It will improve performance in key areas such as secure data transmission, authentication efficiency, and system survivability under contested conditions. By addressing the Navyís need for a secure, distributed, and high-performance computing environment, Z-TAC will directly support critical warfighting capabilities, including AI-driven decision support, autonomous system operations, and secure battlefield communications. In Phase I, Intellisense will design the Z-TAC architecture, including authentication methods, access control policies, and secure communication protocols, to ensure computing hardware in future combat systems is both trustworthy and cyber-secure. Additionally, we will conduct modeling and simulation to evaluate Z-TACís ability to enhance computing infrastructure resilience (CIR) and mitigate supply chain vulnerabilities. To demonstrate the feasibility of Z-TAC, Intellisense will implement a proof-of-concept simulation to validate the integration of authentication mechanisms within UCIe packet structures. We will develop test scenarios to verify secure packet transmission, authentication token validation, and system response to unauthorized access attempts. In Phase II, Intellisense plans to develop and deliver a fully functional prototype of the Z-TAC system based on the architectural design and feasibility results from Phase I. We will conduct rigorous testing across various cybersecurity use cases, demonstrating resilience against supply chain cyber vulnerabilities and ensuring computing hardware trustworthiness in shipboard environments.Ý
Technology keywords
Not reported
Other awards by this recipient
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Awards with the same topic code
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Research funding history
337 SBIR/STTR records share this UEI (2014–2026). Reported award amounts total $162,560,474. Reported amounts are not federal obligations.
Phases: Phase I, Phase II, Phase II – Direct to Phase II
Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Homeland Security, Department of Energy, Department of Commerce, Department of Agriculture
Agency intelligence
Department of Defense
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