SBIR/STTR Research Award

A Cold ASIC for Streaming Readout of Segmented Detectors

Award identifier 993c1a59b0014abcce6c84a3febf1bfd01476d37aee125ecb88ba84d3cb730e7Awarding agency Department of Energy

Award amount

$200,000

Program and phase

SBIR · Phase I

Award year

2024

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Award details

Awarding agency
Department of Energy
Branch
Not reported
Recipient company
PACIFIC MICROCHIP CORP.
Proposal award date
2024-02-12
Contract end date
2024-11-11
UEI
HRMGH9U56EQ1
Solicitation number
DE-FOA-0003110
Topic code
C57-34b

Research abstract

Pacific Microchip Corp. proposes to develop a cryogenic ASIC which includes a 32-channel 12-bit 1GS/s ADC followed by a data processing back-end supporting detector streaming readout. The integrated event building function will compress the data up to 10,000:1 ratio to reduce the interface complexity and power consumption. In the ASICĺs ADC operation mode, the raw data from the 32-channel ADC will be routed out directly through the JESD204B standard compliant data interface. This function is expected to greatly increase ASICĺs commercialization potential. The ASIC will leverage previously developed and silicon- proven IP: a 32-channel 12-bit ADC, an advanced event building function, a CPU, an Ethernet MAC, and interfaces such as a JESD204B, a GTMII and an I2C as well as other blocks. The ASIC will be packaged in ball grid array (BGA) package that was developed for other ASICs and tested. The chip carrier has its temperature coefficient of expansion (TCE) matched with the TCE of the PCB material. This is expected to greatly increase the mechanical reliability of the assembly when it is repeatedly exposed to cryogenic temperatures. Within the proposed project, Pacific Microchip Corp. will prove the feasibility of device implementation (Phase I), design, fabricate and test down to LN2 temperatures (Phase II) a cold ASIC for streaming readout of segmented detectors. In addition to its streaming detector readout and event processing function, the proposed ASIC offers a low- cost, low power solution of a 32-channel 12-bit 1GS/s ADC with the JESD204B standard compliant data interface. The ASIC can find application in imaging systems for airport security, border/customs control, industrial radiography for non-destructive defect detection, radiography in medicine. Cryogenic electronics plays a fundamental role in spacecraft, metrology, superconductive astronomical detectors, and quantum computing. Our ASIC offers these systems to shrink in size, reduce in cost and save power. According to the analysis provided by Future Market Insights, the ADC market is anticipated to reach a value of $3.51B in 2023 and a staggering $6.13B billion by 2033.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

49 SBIR/STTR records share this UEI (2010–2025). Reported award amounts total $21,447,669. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: National Aeronautics and Space Administration, Department of Energy, Department of Defense, National Science Foundation

Agency intelligence

Department of Energy

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