SBIR/STTR Research Award
High Speed Solid State Mass Memory Buffer
Award amount
$69,000Program and phase
SBIR · Phase IAward year
1994Award details
- Awarding agency
- Department of Defense
- Branch
- Navy
- Recipient company
- Controlex Corporation
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- EBJZK4EBABL8
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
The proposal relates to a study leading to the definition of requirements, trade offs and design parameters for a large (144Gb) solid state buffer memory for use in the ATARS and and EO-LOROPS systems. This buffer is intended to relieve operating demands on present digital tape units, so to improve their reliability. The tasks will consider interface requirements from the sensors, optimum architecture, including error management and fault tolerance to achieve high availability in a mission environment. Packaging is also to be addressed; especially important because of the large number of memory chips. Also, under the proposed tasks, a preliminary design for a full-up DEM/VAL buffer will be implemented. A Phase II transition option is offered to prepare a final design for the full-up DEM/VAL buffer.
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- A Very High Speed TeraByte Solid State Mass Memory Implemented with Stacked Die
- A Very High Speed TeraByte Solid State Mass Memory Implemented with Stacked Die
- A Very High Speed TeraByte Solid State Mass Memory Implemented with Stacked Die
- Non-Volatile Solid State Data Recorder For Ultra-High G Environments
- Non-Volatile Solid State Data Recorder For Ultra-High G Environments
Research funding history
7 SBIR/STTR records share this UEI (1994–2012). Reported award amounts total $2,153,608. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense