SBIR/STTR Research Award

SBIR Phase I: TriStar, An Algebraic High Performance Communications Signal Processor

Award identifier 2c094e4610a125728fe09b4ea49b114205d8b30788e1a3c8e01643eb6a90879aAwarding agency National Science Foundation

Award amount

$149,754

Program and phase

SBIR · Phase I

Award year

2010

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
The Athena Group, Inc.
Proposal award date
Not reported
Contract end date
Not reported
UEI
KSLLKKVJYLF9
Solicitation number
NSF 09-541
Topic code
IC

Research abstract

This Small Business Innovation Research (SBIR) Phase I project will research and develop an innovative and revolutionary core wireless infrastructure technology. Wireless technologies impact virtually every aspect of life and require a new high performance, low latency, low power infrastructure technology to move to the next level. Today, communications and digital signal processors (DSPs) achieve high performance levels by creating multi-processor designs; as a consequence, these systems can be overly complex, costly, and power consuming. The proposed project utilizes a high-performance communications and DSP processor design; one based on an understanding of computer arithmetic rather than a massive infusion of hardware. The Phase I project will (1) develop a mathematical framework in which physically realizable multiplier-less TriStar filters and transforms having user defined critical frequency or frequencies can be derived, (2) develop a design methodology that can optimize TriStar solutions for speed, power, complexity and/or latency; and (3) quantify and validate the performance and packaging gains using powerful EDA tools. The hardware implementation of the resulting multiplier-free system will achieve superior performance, cost, and power consumption when compared to today?s best wireless solutions. The broader impact/commercial potential of this project is found in the rapidly increasing $200B (US) wireless market, a market with rapidly increasing technological demands and requirements. The proposed technology represents a major advance in the foundation or infrastructure technology that underlies a wide range of communications, sensor, instrumentation, and telemetry applications. It brings multiple efficiencies to these applications, delivering improved performance, reduced power, reduced silicon area and silicon expense, and run-time reconfigurability. The proposed technology delivers these basic economic justifications while simultaneously delivering such game-changing benefits as extended product life cycle, and improved product performance which can be expressed in attributes consumers prize: longer battery life and faster wireless data rates. Commercial product release will be in a form preferred by the targeted customer-base, namely as semiconductor intellectual property (IP) cores ready for use in semiconductor chip manufacturing. As a result, customers can rapidly and affordably develop and evaluate new wireless solutions and scientific instruments that provide their customers and the public with more affordable, capable, and reliable wireless systems, devices, and accessories.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

56 SBIR/STTR records share this UEI (1987–2018). Reported award amounts total $12,966,391. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, Department of Health and Human Services, National Science Foundation, Department of Homeland Security, Department of Education, Department of Commerce

Agency intelligence

National Science Foundation

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