STAP for an Electronically Scanned Circular Array

The objective of this SBIR project is to produce a single chip GPS receiver using an advanced silicon on sapphire (SOS) technology known as Ultra Thin Silicon (UTSi) CMOS. The chip will be suitable for both commercial and military applications and resultin significant cost (12%), size (up to 70%) and power consumption (up to 50%) reduction compared to current technologies. As a result of discussions with various military customers, this project has been adapted to incorporate anti-jam (andanti-interference) capabilities into the design. Peregrine's design will enable adaptive operation with up to an 82 dB J/S jammer ratio, based on >+30 dBm linearity in the UTSi transistors and integration of 2, 5 and 8 bit A/D converters. The vulnerabilityof GPS to jamming and unintentional interference has become a major concern for both the military and commercial aviation safety. The key deliverable results include novel system architecture, variable bit-width A/D conversion, integrated VCO function,integrated non-volatile memory and a high level of integration of various passive devices. The program will deliver initial measurements of building block circuits fabricated in UTSi upon which the designs will be based. The program options willmanufacture the integrated GPS chip, test the chip and deliver the results. This project will also demonstrate the use of UTSi technology for general use in high integration, single chip radio products.