VERY HIGH SPEED SIGNAL PROCESSOR (VHSSP)

WE WILL PROVIDE EXPERT RESEARCH IN THE PROBLEM OF DEFINING THE VERY HIGH-SPEED SIGNAL PROCESSOR (VHSSP) OPPORTUNITIES INTO THE YEAR 2000 AND BEYOND. THE STUDY WILL INTEGRATE THE EXPERTISE OF NATIONAL SIGNAL PROCESSING LEADERS AND RADC PERSONNEL TO DEFINE POTENTIAL STRENGTHS AND WEAKNESSES IN THE PREDICTED VHSSP TECHNOLOGY BASE. BESIDES STUDYING THE VHSSP ROM A BANDWIDTH STANDPOINT, THE STUDY WILL FOCUS ON THOSE PARAMERTERS WHICH WILL BE REQUIRED IN FRONT-END C3 AND DATA/SENSOR FUSION APPLICATIONS. THESE INCLUDE SIZE, POWER, I/O PARAMETERS, AS WELL AS FAULT-TOLERANCE AND TESTABILITY. TWO POWERFUL INNOVATIVE TECHNOLOGIES WILL ALSO BE INCLUDED IN THE STUDY, BOTH OF WHICH ARE SHOWN TO BE OPTIMAL IN TERMS OF ACHIEVING MAXIMAL BANDWIDTH IN A MINIMAL VOLUME. ONE TECHNOLOGY IS BASED ON THE RESIDUE NUMBER SYTEM (RNS) AND IS FIXED-POINTIN NATURE, THE OTHER IS A FLOATINGPOINT DISTRIBUTED ARITHMETIC PROCESSOR. BOTH ARE POTENTIALLY IDEAL FOR DATA/SENSOR FUSION AND FRONT-END C3 APPLICATIONS. IN ADDITION TO HARDWARE ISSUES, THE STUDY WILL ALSO ADDRESS THE QUESTION OF ELECTRONIC DESIGN AUTOMATION (EDA). FINALLY, THROUGH RESEARCH AND CONSULTATION WITH THE SPONSOR, A PROTOTYPE VHSSP SYSTEM WILL BE PROPOSED FOR DEVELOPMENT OF A CUSTOM VLSI DEMONSTRATION SYSTEM IN PHASE II.