THE ENHANCED SEGMENT INTERCONNECT FOR FASTBUS DATA COMMUNICATIONS-

THE FASTBUS SYSTEM SPECIFICATION FOR HIGH ENERGY PHYSICS AND OTHER DATA SYSTEM APPLICATIONS DEFINES THE SEGMENT INTERCONNECT (SI) AS THE BASIC SYSTEM ELEMENT FOR LINKING BACKPLANE SEGMENTS TOGETHER. THE FASTBUS SPECIFICATION ALSO DESCRIBES A BUFFERED INTERCONNECT (BI) THAT WOULD ALLOW THE HIGHSPEED ACCUMULATION AND STORAGE OF A FASTBUS MESSAGE OR BLOCK OF DATA AND THE SUBSEQUENT FORWARDING OF THESE DATA TO A DESTINATION SEGMENT. THE SI HAS BEEN DEVELOPED AND PROTOTYED, BUT NEITHER THE FASTBUS COMMUNITY NOR COMMERICAL INTERESTS HAVE YET ATTEMPTED TO DEVELOP THE BI. AN ENHANCED SEGMENT INTERCONNECT (ESI) WILL BE DEVELOPED FOR USE IN FASTBUS DATA COMMUNICATIONS AND DATA ACQUISITION SYSTEMS THAT WILL COMBINE THE PROPERTIES OF BOTH THE SI AND BI. BOTH PORTS WILL BE COMPATIBLE WITH THE FASTBUS CABLE SEGMENT AND THE CABLE SEGMENT PROTOCOL; AN OPTIONAL FIBER OPTIC COMMUNICATIONS PORT WILL BE CONSIDERED AS AN ALTERNATIVE TRANSMISSION MEDIUM FOR THE BI. THE COMPANY WILL DESIGN THE ESI WITH ECL SEMICUSTOM INTEGRATED CIRCUITS (IC) TO PROVIDE THE NECESSARY SPACE ON A SINGLE FASTBUS PRINTED CIRCUIT BOARD TO ACCOMMODATE BOTH THE SI AND THE BI STRUCTURES. THIS WILL ALLOW US TO PLACE ABOUT 290 OF THE 320 16-PIN ICS USED TO OMPLEMENT THE PRESENT SI INTO EIGHT TO TEN 68-PIN ARRAYS. THIS DESIGN WILL NOT ONLY MAKE ROOM FOR THE BI CIRCUITRY BUT WILL REDUCE CONSIDERABLY THE ESI'S UNIT COST. THE FEASIBILITY DETERMINATION MADE DURING THE PHASE I RESEARCH WILL INCLUDE A SYSTEM DESIGN OF THE BI PORTION OF THE ESI, SELECTION OF THE ECL SEMICUSTOM DEVICES TO BE USED, A PRELIMINARY PARTITON- ING OF THE SI DESIGN AND BI STRUCTURE TO ENSURE THAT BOTH CAN BE PLACED INTO AN APPROPRIATE NUMBER OF SEMI- CUSTOM IC ARRAYS, AND THE SELECTION OF CANDIDATE CIR- CUITS AND PROTOCOL FOR THE OPTIONAL FIBER-OPTIC BI PORT.