Security Assured Framework for Efficiently Running RTK

To address the Army’s need to run the Army Robotics Common Software (ARCS) software library securely and efficiently on a high-assurance separation kernel, Intellisense Systems, Inc. (Intellisense) proposes to advance the Security Assured Framework for Efficiently Running ARCS (SAFE-RTK), proven feasible during the SAFE-RTK Phase I effort. By leveraging a highly secure microkernel, alongside containerization technology, SAFE-RTK achieves robust isolation of ARCS operations. The ported ARCS/ROS (Robot Operating System) has the following features: (1) cross-platform: new ARCS capabilities can be leveraged by all ARCS-enabled platforms; (2) cross-controller: any ARCS-enabled platform can be controlled by any ARCS-compatible controller; and (3) cross-effort: an effort delivers new capabilities to the ARCS. In addition to memory isolation, the ported ARCS/ROS will be amenable to other security checks such as the concept of Monitor and Policy Enforcement, as applicable and needed in DoD use cases including Autonomy and Swarm. The advantages lie in SAFE-RTK’s ability to efficiently manage resources, deliver consistent performance, and facilitate flexible deployment of robotic applications. This innovation empowers developers to explore the potential of complex robotic systems in a controlled and secure manner, adhering to Army cybersecurity requirements. In Phase I, Intellisense selected the seL4 microkernel and seL4 Microkit framework to build an x86 64-bit hypervisor for Phase II. All design choices, including a representative hardware platform (i.e., the ARM-based ODROID-C4 in Phase I and the x86 based Nuvo-7000LP in Phase II), were made in agreement with the government counterpart. Intellisense finalized the overall design, analyzed the costs and benefits while accounting for practical implementation constraints in Army platforms and use cases, and prepared for a proof-of-concept demonstration. All lessons learned were thoroughly documented. We also explored the path for technology transition to integration on the MRZR platform as well as commercialization paths for memory-safe embedded electronics. In Phase II, Intellisense plans to fully develop the SAFE-RTK technology and produce a practical prototype on x86 hardware. Intellisense will test and evaluate the security and performance of the ported ARCS (and ROS) running on a high-assurance separation kernel using various ROS/ARCS test cases and relevant mission scenarios. Intellisense will also demonstrate the security and performance capabilities under realistic concepts of operations and enhance and mature the technology and prototype for transition. Intellisense is confident that the continued development of the SAFE-RTK technology in Phase II will result in a successful demonstration of SAFE-RTK’s new capabilities using a high-assurance separation kernel, ROS test suite, ARCS applications, and a representative hardware platform under realistic concepts of operations.