High Speed and Ultra Low Power Digital CMOS Circuits with Vdd <0.5V and VT <0.15V

This proposal advocates the use of CMOS circuits with aggressively scaled supply and threshold voltages to design low threshold voltage systems (LVTS) for low power digital applications. The program proposes to generate a CMOS cell library designed around n-channel and p-channel MOS transistors designed to operate at zero threshold voltage, VT=O, using back bias to compensate for process and environmental variations, and improve worst-case performance. This Phase I proposal shows that short channel devices optimized for operation at low supply voltage can achieve excellent performance, provided the threshold voltage is reduced along with the supply. It then demonstrates how the minimum energy and minimum energy-time product depend on logic depth and circuit activity, discusses noise margin issues in circuits operating with very low thresholds, and introduces Ion Ioff as a criterion for maximizing performance at a given supply voltage while maintaining acceptable noise margins. System-level performance and power dissipation of some circuits are extrapolated from measurements of low-threshold devices. The goal of this program is to create a CAD technology base for converting existing conventional CMOS designs to LVTS in Phase I, and transferring the necessary process technology to a commercial CMOS foundry for implementation of an LVTS manufacturing capability in Phase II. LVTS technology combines very low supply and threshold voltages to achieve both high speed and excellent energy efficiency. Implementation of LVTS technology can lead to early energy efficiency gains of 10 to 100 while maintaining comparable performance. This technology scales with the SIA road-map. Future improvements on LVTS CMOS will seek to exploit the synergy between ultra-low-supply voltage and ultra-scaled device dimensions to achieve substantial performance gains as well.