Mapping Complex Sensor Signal Processing Algorithms onto Neuromorphic Chips

The high cost and long timelines for development, testing, and fielding of advanced Radio Frequency (RF) systems (e.g., radar, electronic warfare, etc.) limits the Air Force’s ability to rapidly deploy new capabilities to our warfighters needed to succeed in highly contested RF environments. The problem is further exacerbated by the emergence of sophisticated AI-based capabilities that make the next generation of RF systems, designed to operate in contested environments, even more challenging to test and validate. Lastly, the Air Force’s move to distributed unmanned architectures such as Collaborative Combat Aircraft (CCA) places a premium on low cost, size, weight, and power (C-SWAP). The solution proposed by ISL, whose basic feasibility has been firmly established, addresses all these issues. There is now an opportunity to improve the deployment timeline for new RF algorithms and C-SWAP for embedded processors with the emergence of true neuromorphic commercial hardware chipsets. Neuromorphic hardware (as opposed to hardware that emulates a neuromorphic architecture) has distinct advantages in terms of lower processing power, processing speed, and easier software updates. These commercial neuromorphic Integrated Circuits (ICs) involve many neural elements (or Neural Processing Units (NPUs)) arranged in an architecture that maximizes memory bandwidth using a large number of simple processors, mimicking the architecture of biological brains. They are sometimes referred to as “spiking” NPUs because the signals that travel between NPUs are short-time events. This event-driven processing reduces power consumption by several orders-of-magnitude, as opposed to holding voltages at fixed levels.  The availability of low-power commercial neuromorphic processors represents an opportunity to leverage these ICs to implement conventional RF and radar signal processing algorithms. These commercial chipsets provide workflows to convert existing RF algorithms onto the neuromorphic architecture(s). Previous work conducted by ISL has firmly established the efficacy of this approach by leveraging ISL’s RFView family of Digital Engineering (DE) tools (see https://www.islinc.com/products/rfview).  ISL is well-positioned to succeed on this proposed effort. ISL has a long history of using site-specific clutter modeling techniques (both off-line and real-time) to develop and validate neural network models. ISL’s staff includes internationally known subject matter experts (SME) in neural network architectures who will provide critical domain knowledge to ensure that the developed approach will meet current as well as future AF T&E requirements. ISL also maintains classified computing facilities that can be used to perform model validation. These factors put ISL in a unique position to succeed under the proposed SBIR project.