SBIR/STTR Research Award

Scalable Data Acquisition System for MKID Detectors

Award identifier 0eadf458faabbc2c8c61a43ebe759fa144575f6dc52660c4c7a326652e190620Awarding agency National Aeronautics and Space Administration

Award amount

$896,222

Program and phase

SBIR · Phase II

Award year

2024

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
Alphacore, Inc.
Proposal award date
2024-07-27
Contract end date
2026-07-26
UEI
CXMPDDLFBCH3
Solicitation number
SBIR_23_P2
Topic code
S11

Research abstract

Alphacore is developing a low cost, scalable data acquisition system (SDAS) centered around an innovative application-specific integrated circuit (ASIC) for Microwave Kinetic Inductance Detectors (MKIDs). The SDAS ASIC will have 14 bits for digitization (Analog to Digital Conversion ndash; ADC) and 14 bits or more precision for carrier tone generation (Digital to Analog Conversion ndash; DAC), with each channel handling gt;4GHz of bandwidth (instantaneous bandwidth of gt; 8GHz at 4GS/s per ASIC and tunable bandwidth range of 16GHz) along with an on-chip low jitter PLL while consuming very low power per detector readout chain.nbsp; In Phase I we successfully optimized, fabricated, and tested high-speed, low-power 5GS/s ADC and DAC CMOS designs, proving functionality of the chips at room temperature and pre-irradiation, completed radiation testing, and developed strategies include a sophisticated model for improving the radiation tolerance of the parts. The single-channel SDAS ASIC prototype complete system was successfully integrated using optimized ADC, DDS and interface with DSP. Full radiation testing of the ADC was also completed with very successful results: it was established that these designs clearly meet the hardness requirements of the target missions. The ADC and DAC designs are silicon tested and optimized for resolution. A second tapeout is scheduled in Feb 2024 (using Alphacorersquo;s internal funding) that will easily surpass NASA requirements. Firmware including RTL code for AMD/Xylinx Ultrascale MPSoC has been developed and hardware demonstrated. A combination of low power, time-interleaving ADC/DACs with innovative calibration architectures enabled Alphacorersquo;s designs to achieve high frequency operation at high resolution while consuming ultra-low power. Current estimation of total power, including the MPSoCrsquo;s FPGA computation, is less than 5.2W/1GHz, which will also be improved in Phase II.nbsp; nbsp;

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

155 SBIR/STTR records share this UEI (2013–2026). Reported award amounts total $63,784,604. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Energy, Department of Commerce

Agency intelligence

National Aeronautics and Space Administration

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