SBIR/STTR Research Award

Ultra-wideband High Efficiency Power Amplifier for Multifunction RF Systems

Award identifier ac05377dc8c0bc4440633bc85fb6e1dadc7916082ccfae78c956d2e37efc3e8cAwarding agency Department of Defense · Air Force

Award amount

$1,249,793

Program and phase

SBIR · Phase II

Award year

2024

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
ENGIN-IC INC
Proposal award date
2024-07-24
Contract end date
2026-10-24
UEI
J4LWTAZLK4Q9
Solicitation number
22.2
Topic code
AF222-0020

Research abstract

ENGIN-IC will implement the Phase 1 designed wideband, GaN-on-SiC high efficiency amplifier to achieve the goals of this program.  ENGIN-IC applies a novel, patented circuit topology to achieve simultaneous high output power, low SWR, and high PAE load impedance match across a decade bandwidth or more.  The circuit topology proposed is quite different from that of a distributed amplifier.  The feedback topology proposed enables higher amplifier PAE across a wide bandwidth, and greatly reduces the size of the amplifier in comparison to distributed amplifier circuit topologies.  Such amplifiers can then be sized easily to fit in 3 mm or smaller array spacings and provide high gain, reducing the requirements for driver amplifiers.   ENGIN-IC has built more than 10,000 3-W, 33% PAE 2 – 18 GHz GaN amplifiers over the past four years.  Amplifier dimensions are 4.2 mm x 1.7 mm – the parts are very narrow in width, and support T/R element spacings of 3 mm or less.  These amplifiers offer 31-dB small-signal gain and 13-dB or better I/O return loss across 2 to 18 GHz.  This production experience forms a strong foundation for the proposed study and development work for this AFRL high PAE amplifier program.  A two-stage, 2 to 20 GHz GaN amplifier has been demonstrated by ENGIN-IC this past year, offering 1.6-W output power and 47% average PAE across the band.  This amplifier has been measured at AFRL and ENGIN-IC.  This has set a new efficiency record for near decade bandwidth solid-state amplifiers in this frequency range.  Based on the study work completed in Phase 1, ENGIN-IC will be able to increase both output power and efficiency of the amplifier to meet the program objectives of Phase 2. ENGIN-IC has done design work in eight GaN foundry processes and selected two processes for the design of the SSPA.  ENGIN-IC expects both foundry solutions to realize excellent performance and at the end of Phase 2, ENGIN-IC will demonstrate an amplifier that achieves >2 W Pout, more than 20 dB gain, and near 54% average PAE, and minimum PAE of 50% across 2 to 18 GHz, at room temperature.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

16 SBIR/STTR records share this UEI (2015–2024). Reported award amounts total $7,853,675. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense

Agency intelligence

Department of Defense

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