Ga2O3-AlN Heterojunction Epitaxy using Low-Temperature Plasmas

Our team of small business and DOE National lab researchers proposes to utilize low temperature plasmas to advance Gallium Oxide (Ga2O3) semiconductor materials and establish a new performance standard for high power transistors. While Gallium Oxide transistors can sustain higher breakdown voltages than more common transistors made from Silicon Carbide (SiC) or Gallium Nitride (GaN), these oxide-based semiconductors are not commercially useful due to (1) problems in the epitaxial growth of these semiconductors to be solved using low temperature atomic O plasma, and (2) their low thermal conductivity. Our work will focus on a new Gallium Oxide - Aluminum Nitride (AlN) transistor structure. AlN has a very high thermal conductivity, allowing our new transistor structure to conduct the heat away from the Ga2O3 power transistor layer. We intend to advance the semiconductor growth for power transistors by utilizing an advanced high-flux/ high-purity energetic Oxygen/Nitrogen atom source developed at the DOE National Lab that can switch rapidly between Oxygen and Nitrogen. Our e?ort will initially focus on Ga2O3 transistor epilayer growth on 2-inch diameter sapphire substrates that contain thick AlN bu?er layers. After the initial demonstration of the technology on 2-inch wafers during Phase I, we will transition to wafer growth on 100mm diameter substrates in the Phase II program using a Wafer Production Cluster Tool owned by the small business. A significant materials characterization e?ort will support the Phase I Ga2O3-on-AlN transistor program, including X- Ray Di?raction to verify crystal quality, Hall Measurement to determine carrier mobility, Capacitance Voltage measurements, electrochemical Capacitance Voltage profiling to map carrier concentration as a function of depth into the structure, and non-contact resistivity measurement. We would expand our e?ort in Phase II to include photoluminescence measurements. After the initial materials growth demonstration is established during Phase I, our materials characterization plan during Phase II shall include rapid device fabrication and measurements at OSEMI with Transmission Line Measurements to characterize ohmic contact resistance and DC and Pulsed IV measurements to document baseline Radio Frequency (RF) and fast-switching behavior of these new transistors. Deliverables for Phase I shall include technical data in reports, sample epitaxial wafers, and processed wafers containing microelectronic device structures. The primary goal of this program is to provide the United States and domestic electronics device makers with a next-generation high-performance transistor structure useful generally in high voltage electric energy applications such as solar, wind, and high power electronics including power supplies and electric vehicle charging at substantially higher voltages than GaN or SiC can currently achieve. A second goal is to provide DOE and the greater High Power Electronics maker ecosystem community with a new highly controllable and commercially reliable process methodology within a US-based semiconductor foundry to manufacture these new transistor structures for the benefit of American manufacturers and consumers. A third and final goal will be to provide DOE and DOD Prime Contractors with a new qualified supplier of 100mm diameter Ga2O3-on-AlN transistor semiconductors by the end of the Phase II program that is anticipated to provide a benefit to US Energy e?ciency and US National Defense.