SBIR/STTR Research Award

Critical Logic Erasure for Abandonment of Non-Sanitized Equipment

Award identifier 38e7de035b7497dbba6d439408edddd5a4aeffb0828c4d0e1cb2fef07372844aAwarding agency Department of Defense · Army

Award amount

$1,299,991

Program and phase

SBIR · Phase II – Direct to Phase II

Award year

2024

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Award details

Awarding agency
Department of Defense
Branch
Army
Recipient company
INTELLISENSE SYSTEMS INC
Proposal award date
2023-11-30
Contract end date
2025-12-02
UEI
C4Y5CNN55L37
Solicitation number
23.4
Topic code
A234-018

Research abstract

To address the ArmyÆs need for secure field-programmable gate array (FPGA) erasure for U.S. military systems abandoned in theater, Intellisense Systems, Inc. proposes to develop a new Critical Logic Erasure for Abandonment of Non-Sanitized Equipment (CLEANSE) technology. Specifically, the innovation in CLEANSEÆs FPGA erasure strategy for programmable military assemblies will improve the security of programmable devices and prevent foreign entities from being able to reverse engineer sensitive U.S. military equipment. As a result, this technology can be implemented into legacy line-replaceable units (LRUs), units under repair, and future LRUs, which directly addresses the Army requirements to secure FPGAs and systems on a chip (SoCs) with a unique erasure strategy. Intellisense has a comprehensive suite of FPGA-based military electronics and intellectual property (IP) to demonstrate feasibility of the technology capable of showing how current general-purpose FPGA-based systems and design logic can be adapted to integrate the erasure capability with minimal-to-no impact to LRU size, weight, and power. In support of this proposed technology, we analyzed the CLEANSE solution and evaluated the viability of the proposed erasure solution for military, medical, and commercial applications, including addressing the DoDÆs move toward Modular Open Systems Approach requirements. In Phase II, Intellisense plans to implement CLEANSEÆs logic design from a military ground vehicle on an FPGA or SoC to demonstrate erasure in an LRU such as a display. The addition of military-grade encryption will also be introduced to the CLEANSE design. Implementation of established requirements to the CLEANSE IP, such as a unified (FPGA or software-based solution) vendor-agnostic IP solution, are also proposed. Intellisense will develop and refine our business model to be ready for marketing the proposed system to commercial vendors where data security is a top priority for an organization and its products.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

337 SBIR/STTR records share this UEI (2014–2026). Reported award amounts total $162,560,474. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Homeland Security, Department of Energy, Department of Commerce, Department of Agriculture

Agency intelligence

Department of Defense

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