SBIR/STTR Research Award

Radiation Hardened ASIC for Control of Amplitude and Frequency Modulated Inertial Sensors

Award identifier 6eff39d2e53adca326f35cd4bd450287cc8a5fdcb1d9512f6ef47fb25c7962feAwarding agency National Aeronautics and Space Administration

Award amount

$149,704

Program and phase

SBIR · Phase I

Award year

2023

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
INERTIALWAVE INC
Proposal award date
2023-08-01
Contract end date
2024-02-02
UEI
GRH5KCAFEXE3
Solicitation number
SBIR_23_P1
Topic code
S16

Research abstract

A Universal Resonator Controller (URC) ASIC is proposed, primarily to measure inertial sensors.nbsp; High performance, navigation-grade IMUs use discrete parts to sense accelerometers and gyroscopes.nbsp; By using ASICs instead of COTS ICs IMU size and power consumption can be reduced.nbsp; A major issue in both rad-hard and terrestrial IMU markets is the lack of volume for high-performance systems when spread out across many players.nbsp; It is not particularly feasible to develop a cutting-edge product with all the difficulties of an ASIC for a single specific sensor.nbsp; Instead, the URC casts a wide net, allowing integrators to pick and choose which sensors to interface with.nbsp; With only a handful of passives and support ICs, the proposed URC would be able to operate with most inertial sensors operating with resonant frequencies between 5kHz-150kHz.nbsp; Nearly any resonating system may be controlled or sensed with this architecture due to its flexible digital programmable settings and selected external passives.nbsp; A prototype with limited bandwidth and only amplitude modulation has been developed. nbsp;Both voltage and current transduction modes are already available.nbsp; Phase I efforts will be dedicated to improving and implementing targeted innovations.nbsp; Due to the duration of work and award amount Phase I focuses on simulation and selected transistor-level designs.nbsp; Radiation hardening methods will be simulated, ADC bandwidth improved, and frequency demodulation architectures designed.nbsp; The existing ADC will be migrated to a rad-hard process and architecturally improved to guard against SETs.nbsp; Phase II will then proceed with full chip design and migration efforts, culminating in the tapeout of a wide bandwidth, rad-hard URC ASIC with best in-class SWaP.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

7 SBIR/STTR records share this UEI (2015–2025). Reported award amounts total $3,172,214. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration

Agency intelligence

National Aeronautics and Space Administration

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