SBIR/STTR Research Award

High Performance Analog to Digital Converter for Deep Cryogenic Instrumentation

Award identifier e68ea64552133511d1e1858acadbd9a2b7187a95b7a68447733d2d26bb94efd5Awarding agency Department of Energy

Award amount

$199,997

Program and phase

SBIR · Phase I

Award year

2023

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Award details

Awarding agency
Department of Energy
Branch
Not reported
Recipient company
PRIXARC LLC
Proposal award date
2023-07-10
Contract end date
2024-04-09
UEI
F4N3H1J8CDC8
Solicitation number
DE-FOA-0002903
Topic code
C56-37c

Research abstract

Prixarc will develop and commercialize a cryogenic multi-channel (16 channels) analog to digital converter (ADC) with moderate speed (= 1MHz sampling rate) and high resolution (=14-bit) for high energy physics (HEP) applications fabricated in a complementary metal oxide semiconductor (CMOS) process and to potentially operate down to ambient temperatures of ~50mK. We propose to implement the ADC using fully depleted silicon-on-insulator (FDSOI) CMOS process. The main deleterious effects of cryogenic operation with transistors fabricated in CMOS processes include a moderate increase in threshold voltage and degradation in 1/f noise and matching properties, both of which can be overcome using well-known precision circuit design techniques and using FDSOI process nodes. FDSOI process helps to reduce parasitic capacitance, which reduces power consumption (thus, reducing self-heating), allows for back-biasing to actively trade off power consumption and performance, and reduces temperature dependency due to less doping.During Phase I, we will study ASIC design and fabrication considerations for extreme low-temperature operation. We will device a cryogenic Successive Approximation Register (SAR) ADC with calibration. We will develop transition plan/business case analysis. We will identify technological and reliability challenges of our design approach and propose viable risk mitigation strategies. The circuit design and simulation results will be our key deliverable. Following Phase I, the most promising ADC design will be further refined, fabricated, and tested in Phase II and offered as an integrated hardware module.Integrating ADCs in the cryogenic systems will significantly improve signal integrity. The high-performance cryogenic ADC is useful for many commercial and government applications in HEP, spacecrafts, satellites, medical imaging, defense and aerospace, and quantum computing. For DOE, the Deep Underground Neutrino Experiment (DUNE) requires a high-resolution ADC to operate at cryogenic temperature. For NASA, the temperatures at the poles of Mars and in permanently shadowed craters on the Moon can reach below 130K, temperatures at the surface of Titan can reach as low as 90K, and deep-space systems, e.g., the detector electronics of the James Webb Space Telescope, operate at low cryogenic temperatures. For commercial applications, electronic components are intentionally cooled to improve system sensitivities, e.g., in medical imaging.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

17 SBIR/STTR records share this UEI (2018–2024). Reported award amounts total $6,275,539. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Energy

Agency intelligence

Department of Energy

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