SBIR/STTR Research Award

High-Channel Count, Picosecond Timing Resolution and Extreme Radiation Hardness Time to Digital Converter

Award identifier 08eb5726109aad806dfa448ae5ec837a5174413fb0482055781b5c30776ef8aaAwarding agency Department of Energy

Award amount

$199,936

Program and phase

SBIR · Phase I

Award year

2022

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Award details

Awarding agency
Department of Energy
Branch
Not reported
Recipient company
PRIXARC LLC
Proposal award date
2022-06-27
Contract end date
2023-03-26
UEI
F4N3H1J8CDC8
Solicitation number
Not reported
Topic code
C54-33e

Research abstract

Prixarc will partner with Alphacore Inc. to develop and commercialize high-precision, high-resolution, and high-channel count timing measurement systems for next generation detectors in high energy nuclear physics experiments. We will develop a custom Application Specific Integrated Circuit (ASIC)-based 64-channel Time to Digital Converter (TDC) with RMS time precision better than 10 ps, operational temperature range from 77 K to 300 K, and radiation hardness to 100 Mrad (Si) using Skywater Technology RH90nm FDSOI CMOS process. General statement of how this problem is being addressed. The proposed TDC with high time precision, high radiation hardness, and high channel count is possible because of two novel aspects: (i) stochastic TDC design [Radiation Hardened by Design (RHBD)] and (ii) a fully depleted silicon-on-insulator (FDSOI) complementary metal–oxide–semiconductor (CMOS) fabrication process [Radiation Hardened by Process (RHBP)]. What is to be done in Phase I? During Phase I, we will study ASIC design and fabrication considerations for extreme radiation and low-temperature operational environments. We will device a stochastic TDC architecture with self-calibration. We will develop transition plan/business case analysis. We will identify technological and reliability challenges of our design approach and propose viable risk mitigation strategies. The circuit design and simulation results will be our key deliverable. Following Phase I, the most promising TDC design will be further refined, fabricated, and tested in Phase II and offered as an integrated hardware module. Commercial Applications and Other Benefits (limited to the space provided). The TDC will play an increasingly important role in the nano-CMOS era, because it is well suited to implementation with nanoscale digital CMOS processes. The proposed high-performance TDC and processor is useful for a variety of applications in spacecrafts, satellites, communications, medical imaging, electronic warfare, and photonic integrated circuits. The success of this project will lead to high performance TDC systems that can be applied to both consumer/industrial applications and specialized radiation environments for nuclear physics applications. In addition, the proposed work would utilize new domestic U.S. based CMOS process for development and manufacturing of next generation radiation hardened and cryogenic integrated circuits.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

17 SBIR/STTR records share this UEI (2018–2024). Reported award amounts total $6,275,539. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Energy

Agency intelligence

Department of Energy

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