A Signal Frequency Channelizer ASIC

Far infrared and sub-mm astronomy instruments employ MKIDs for measurements of ultimate sensitivity and resolution exceeding 10,000 pixels. Detector array readout requires RF frequency division multiplexing and complex multichannel signal processing. An off-the-shelf ADC in combination with an FPGA based DSP block used for spectrum channelizing and power level measuring in each frequency bin suffers of unacceptable system size, weight and power (SWaP).We propose to develop an ASIC which will channelize signal spectrum into 2048 frequency bins. These bins can be tuned with 0.954KHz per bin resolution to any portion of the spectrum within -500MHz to +500MHz. The ASIC will include two 12-bit 1GS/s ADCs, a data alignment and demultiplexing block, 2048 DFT cells, an accumulation/readout block and a high-speed Ethernet interface. Additionally, the ASIC will include a PLL for clock synthesis, a debug memory for storing of short duration raw digitized data or debug data from the DSP block. A digital control subsystem will handle the entire ASICrsquo;s operation and communication. In addition to minimized SWaP, the ASIC will tolerate TID and SEE. Within Phase I, we proved the ASIC implementation feasibility. Phase II will result in the silicon proven ASIC prototypes.