SBIR/STTR Research Award

A High Channel Density Digital Acquisition System

Award identifier 0331cf33bbc3164b7be7c72f3aa7432be71afcd42818de44a8ff20a8a4e3c9aeAwarding agency Department of Energy

Award amount

$200,000

Program and phase

SBIR · Phase I

Award year

2023

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Award details

Awarding agency
Department of Energy
Branch
Not reported
Recipient company
PACIFIC MICROCHIP CORP.
Proposal award date
2023-02-21
Contract end date
2024-02-20
UEI
HRMGH9U56EQ1
Solicitation number
Not reported
Topic code
C55-22a

Research abstract

Nuclear physics (NP) experiments require large channel count detectors to accurately monitor, or trace events induced by sub-atomic particles. Gamma- and X-ray imaging and spectroscopy instruments are frequently utilized to detect, localize, and characterize nuclear materials, photons, or particles of light. These detector systems include a large number of simultaneously working detector elements. The challenge is to properly address the need of large channel count, high-precision and high-speed data acquisition (DAQ) system for such a densely populated detector system. Pacific Microchip Corp. proposes to develop a 256-channel data acquisition (DAQ) system based on a 32-channel 12-bit 0.5GS/s ADC ASIC developed under the DoE SBIR award DE-SC0017213. This ADC ASIC also includes a PLL clock synthesizer to generate a low-jitter sampling clock on-chip (a single reference clock is used for channel synchronization of the proposed DAQ system), a JESD204B standard compliant high-speed data interface, an I2C interface for programming configuration registers and precision low-noise biasing circuits. Eight ADC ASICs are required for 256 acquisition channels. A commercial Virtex Ultrascale FPGA will receive data from two ADC ASICs – a total of 64 data lanes each running at 8Gb/s. The FPGAs will also implement custom digital signal processing (DSP) and high-speed data transmitting. A QSFP+ transceiver is used to transform the electrical 4x10Gb/s data from FPGAs to the optical mode and transmit it through a single optical fiber at aggregate 40Gbps. In Phase I, we will provide the proof of implementation feasibility for a 256-channel DAQ system based on the Pacific Microchip Corp.’s 32-channel ADC ASIC. Phase II project will result in the improved performance ADC device and a fabricated and tested complete 256-channel data acquisition system. According to the latest market study released by MarketsandMarkets, the data acquisition market is projected to reach USD 2.3 billion by 2026 from USD 1.7 billion in 2021, at a CAGR of 5.5%. Examples of commercial applications for the proposed DAQ system include imaging systems for airport security, border/customs control, industrial radiography for non-destructive defect detection, radiography in medicine. Currently, there is no DAQ system able to perform 256-channel data acquisition with 12-bit 500MS/s ADC per channel followed by commercial FPGAs for digital signal processing. The status of market lead in providing the DAQ system for detector signal processing will contribute to the success of our product.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

49 SBIR/STTR records share this UEI (2010–2025). Reported award amounts total $21,447,669. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: National Aeronautics and Space Administration, Department of Energy, Department of Defense, National Science Foundation

Agency intelligence

Department of Energy

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