Low Temperature Plasma Enhanced Processing for Microelectronics Manufacturing

In this SBIR/STTR proposal, an innovative low temperature annealing processing technology will be developed for the applications of: Advanced Semiconductor CMOS low temperature dopant activation. Post integrated circuits (ICs) or charge-coupled devices (CCDs) processing, including the formation of PN junction on the back side of wafers. Advanced annealing or formation for metal, biochemistry, or other new materials. Current, commonly used annealing processes for dopant activation require temperatures higher than 400°C. For future advanced microelectronics, nanotechnology, and biotechnology applications, lower process temperatures are needed. In this proposal, a low temperature annealing technology will be developed based on innovative multiple energy sources processes. The technique combines several sources of energy to achieve high-level dopant activation at low temperatures. This process is compatible with integrated circuit sensor fabrication. In Phase I, we will develop surface energy enhanced microwave annealing recipes under 400C; ion-implanted wafers will be used to characterize the dopant activation level and the junction leakage current. Double-sided wafers will be processed to evaluate the impact of post-CMOS annealing on front side transistor integrity. After phase I, the company will work with semiconductor equipment company to co-develop commercial equipment. The wafer demo and equipment field testing will be performed in phase III commercialization. The broad areas of application for this low temperature technology include the internet of things (IoTs), supply chain management, industrial process monitoring, security and surveillance, health/medical monitoring, remote and hazard