SBIR/STTR Research Award

Heterogeneous computing system with dynamic fault tolerance to radiation harden commercial microelectronics (Hetero-Hard)

Award identifier 4eac320c85e09061af32f595be1d68cc2b8e77d7718812d76e53bbe35fcd5c91Awarding agency Department of Defense · Missile Defense Agency

Award amount

$149,912

Program and phase

SBIR · Phase I

Award year

2022

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Award details

Awarding agency
Department of Defense
Branch
Missile Defense Agency
Recipient company
CFD Research Corporation
Proposal award date
2021-12-06
Contract end date
2022-06-05
UEI
V3KCP1HNFM33
Solicitation number
21.2
Topic code
MDA21-022

Research abstract

In this work, we propose a heterogenous computing system which can seamlessly integrate with the commercial off the shelf (COTS) part and provide design hardening against radiation without modifying the inherent design of the COTS part. The heterogenous computing system will employ an in-situ radiation monitoring system and dynamic fault tolerant system, which will be designed using the vendor provided information of the COTS part. Also, since these systems are like add-ons and not part of the COTS part’s circuit design, the effect on inherent performance characteristics of the COTS part will be minimal. In Phase I, we will focus on the base design of proposed heterogenous computing system using a digital COTS part as circuit under test (CUT). We will work closely with University of Tennessee at Chattanooga (UTC) to design and implement tests and validations to prove the validity of the proposed system. A machine learning based intelligent mathematical model will be designed to monitor radiation effects in COTS CUT. A selective redundancy-based fault tolerance model will be designed to dynamically mitigate radiation effects. Finally, the individual modules, radiation monitor, fault tolerance, will be integrated using a heterogenous computing system that utilizes Graphic Processing Unit (GPU) and Field Programmable Gate Array (FPGA). In Phase II, we will focus on the optimization of the proposed methodology by adjusting the design to achieve desired performance. We will expand the proposed system’s capability to address an analog circuit block. Prominent analog COTS parts like analog-to-digital and digital-to-analog converters (ADC/DAC) will be used as CUT, and the proposed system and its modules will be tested and validated. The comprehensively optimized system will be fabricated and tested with physical COTS parts. Approved for Public Release | 21-MDA-11013 (19 Nov 21)

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

947 SBIR/STTR records share this UEI (1987–2026). Reported award amounts total $350,893,199. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Health and Human Services, National Science Foundation, Department of Commerce, Department of Energy

Agency intelligence

Department of Defense

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