Error Detection and Latch-up Prevention in Radiation Hardened Logic Units

Peripheral microelectronic components within a heterogenous substrate system in package (SIP) design will be outfitted with both a Latch-up Protection and Recovery Circuit (LPRC) and a logic Error Detection and Correction (EDAC). The LPRC will have a supervisory role in detecting chip malfunctions and taking corrective actions. Single Event Latch-up (SEL) caused by Single Event Upset (SEU) can be monitored by current flow measurements and corrected by enacting a soft reboot of both central and peripheral components, as required. Commercial Off The Shelf (COTS) Integrated Circuits (IC) are available in radiation tolerant forms and can be used to construct an LPRC that will not malfunction alongside other components during SEUs. A redundant duplicate architecture will also be used to detect and correct logic errors caused by SEU. Built-in Error Correction Code (ECC) will be implemented in Static random-access memory (SRAM) units to prevent the alteration of stored bits by ionized particles. The LPRC and EDAC circuits can be constructed from Bipolar Junction Transistors (BJTs) and passive components. While bipolar junction transistors (BJTs) can suffer from the effects of radiation, the supporting circuitry can be designed to derate PNP and NPN transistors by 10x to 100x in order to meet sufficient performance even when the BJTs are exposed to Total Ionizing Doses (TIDs) of up to 300 krads. Approved for Public Release | 21-MDA-11013 (19 Nov 21)