Robust Radiation Hard Low Power DAC

Adsantec will design and fabricate a Digital-to-Analog Converter (DAC) as a single-package Application Specific Integrated Circuit, (ASIC) capable of surviving and maintaining performance in high radiation environments (gt; 1 Mrad), including enhanced low dose rate sensitivity.nbsp; The DAC will have a sampling rate greater than 2 Gb/s with effective number of bits gt;10. The design will be based on the companyrsquo;s proprietary reconfigurable DAC architecture, which incorporates a patented Pseudo Straight Forward Synchronization algorithm (PSFS), a patented rad-hard Clock Recovery scheme and a proprietary rad hard Serial Peripheral Interface. It will allow direct interfacing with a variety of Field Programmable Gate Arrays (FPGA) used by NASA and other space customers. The robust DAC architecture will incorporate both serial and parallel FPGA to DAC interconnectThe proposed PSFS will be implemented inside the developed ASIC minimizing overhead during data transmission. In this design, ADSANTEC will employ proven SiGe bipolar transistor-based circuit blocks based on our rad hard-by-design methodology. The use of ADSANTECrsquo;s space qualified ASIC packaging will enable fabrication and test of the DAC with TRL 7 or higher ASIC prototype at the end of Phase II.