SBIR/STTR Research Award

Design and fabrication of the HDSoC- High Density digitizer System-on-Chip

Award identifier c560e02aab444396da3f8cc5d0384f6ce2165e562b717005db41257a2ce7e840Awarding agency Department of Energy

Award amount

$1,149,994

Program and phase

SBIR · Phase II

Award year

2021

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Award details

Awarding agency
Department of Energy
Branch
Not reported
Recipient company
NALU SCIENTIFIC, LLC
Proposal award date
2021-05-03
Contract end date
2023-05-02
UEI
ZFYUKU9F8TQ4
Solicitation number
Not reported
Topic code
32b

Research abstract

Nalu Scientific will develop the “HDSoC,” a fast integrated circuit to readout several (up to 64) high-speed signals generated by particles in nuclear and high energy physics experiments. Detection of individual charged particles and photons and estimation of their properties is the basis for a wide range of scientific and commercial applications from high-energy, nuclear, and astrophysics to medical imaging and diagnosis and LiDAR. We are targeting the data acquisition market for medium to large scientific experiments in the energy or intensity frontiers. These complex experiments require hundreds to thousands of recording channels at high samplings speed and high rates capable of fast data acquisition and signal processing. The HDSoC allows for timing resolutions on the order of 100s of picoseconds, translating to highly accurate estimates of charged particles and their tracks. Low cost, low power designs are especially attractive for experiments with thousands of recording channels. We propose to design and make commercially available the “HDSoC”: a low-cost, low-power, high-density waveform sampling chip capable of analog signal conditioning, fast waveform sampling, and integrated readout. The 64-channel HDSoC device will also be capable of controlling sensor biases and perform on-the-fly feature extraction to optimize the readout efficiency for high density detectors, making it suitable for large Nuclear Physics experiments with high trigger rates. We designed a full 32-channel HDSoC chip satisfying the specifications, thus demonstrating the feasibility of the project. The chip will be available for testing at the beginning of phase II. We will test performance and redesign for robustness, fabricating several revisions of the prototype and incrementally add features until the desired 64 channel chip is created. This device can be used by scientists in high energy and nuclear physics experiments for fast analog data acquisition. It also has applications in high-end general-purpose instrumentations, medical/PET imaging, automotive and remote sensing (self-driving vehicles) with LIDAR. We anticipate the ability to sell the device as an OEM manufacturer, provide associated design services or license it to a larger device manufacturer due to the low cost and low power nature of the design, giving us a competitive edge.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

33 SBIR/STTR records share this UEI (2016–2025). Reported award amounts total $14,748,717. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Energy, National Aeronautics and Space Administration, Department of Health and Human Services, Department of Defense, Department of Commerce

Agency intelligence

Department of Energy

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