OPIR Processing Testbed: In-Flight Optimization of New Algorithms (OPTION-A)

On-board processing is crucial to the future of warfighting in space. The number of sensors – and the quantity of data collected by each sensor- is increasing to meet the demand for persistent, resilient, and capable global target detection and tracking. Emerging threat capabilities drive the need for super low-latency data transport to the tactical edge and automated decision making. Current downlink data rates cannot keep up with the proliferation of data. Reconfigurable on board processing is the critical warfighting enabler, and, fortunately, the capability of space-qualified hardware is increasing. New SoC systems have faster CPUs and more accelerators like GPGPUs and FPGAs than would have been imaginable five years ago. This hardware can support the computationally intensive advanced algorithms necessary to address the challenge – if you know how to develop for it. SciTec proposes “OPTION-A” – OPIR Processing Testbed: In-Flight Optimization – to demonstrate the necessary technologies and feasibility for a universal development environment on low size, weight, power, and cost (SWAP-C) on-board processing systems. This effort will create a user-friendly OPIR development environment to streamline the on-board development process, allowing for more resources to be spent on developing, tuning, and optimizing OPIR algorithms.