SBIR/STTR Research Award

Military Equipment Abandonment Solution for Programmable Assemblies

Award identifier daa38dc5db08d070624d7662bc2048d31edfd0e4550665f5becb81aaec6bdd7eAwarding agency Department of Defense · Army

Award amount

$111,497

Program and phase

SBIR · Phase I

Award year

2020

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Award details

Awarding agency
Department of Defense
Branch
Army
Recipient company
INTELLISENSE SYSTEMS INC
Proposal award date
2020-06-26
Contract end date
2021-06-08
UEI
C4Y5CNN55L37
Solicitation number
20.1
Topic code
A20-099

Research abstract

To address the Army’s need for secure Field Programable Gate Array (FPGA) zeroization for U.S. Military systems abandonment in foreign land, Intellisense Systems, Inc. proposes to develop a new Military Equipment Abandonment Solution for Programmable Assemblies (MEASPA). Specifically, the innovation in the FPGA zeroization strategy for programmable military assemblies will improve the security of programmable devices and prevent the risk of foreign entities being able to reverse engineer U.S. Military sensitive equipment. As a result, this technology offers a solution that can be implemented into legacy Line Replaceable Units (LRU), units under repair, and future LRUs, which directly addresses the Army requirements to secure FPGAs with a unique zeroization strategy. In Phase I, Intellisense will conduct a feasibility study through research on how current general-purpose FPGA boards and design logic can be adapted to the proposed design. We will analyze the MEASPA solution with simulations and hardware demonstration and evaluate the viability of the proposed zeroization solution for military, medical, and commercial applications. In Phase II, Intellisense plans to implement MEASPA’s logic design from a military ground vehicle on an FPGA platform (i.e., Altera or Xilinx) to show a proof-of-concept prototype, and create design logic for an FPGA using respective FPGA environments. This logic will implement a system’s design that meets military data encryption standards. Intellisense will also create software that can synthesize the FPGA logic with a zeroized design if given a command to do so. At the end of Phase II, Intellisense will have a working prototype of the MEASPA system. We will also have a business model ready for marketing the MEASPA system to commercial vendors.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

337 SBIR/STTR records share this UEI (2014–2026). Reported award amounts total $162,560,474. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Homeland Security, Department of Energy, Department of Commerce, Department of Agriculture

Agency intelligence

Department of Defense

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