Secure FPGA Zeroization for Military Systems Abandonment

Deployment of sensitive electronic systems requires the assurance that intellectual property and critical security parameters are protected even when the system falls beyond the control of authorized users. FPGAs enable deployment of low-SWaP systems without the exorbitant costs and schedules of ASIC development, while improving their security by utilizing zeroization to cleanse all configuration and operational data. Ensuring a thorough cleansing of the FPGA-based system requires the system designer to carefully consider the details of the target FPGA vendor and platform. We propose a better approach that encapsulates those details and presents a standard interface to allow rapid and secure destruction of all sensitive data associated with the FPGA. The result enables system designers to quickly develop and deploy high-security, low-SWaP electronic systems without regard to the details of the target platform. The initial phase will research the capabilities and requirements of zeroization for general-purpose COTS FPGA systems, define a standard interface for integration of these capabilities into a target system design, and demonstrate a proof-of-concept implementation of that interface on a development platform. The goal of this work is to deliver a platform-agnostic framework for implementation of secure FPGA system zeroization that can be quickly integrated into target designs.