RF SIGNAL DIGITIZER WITH SPUR ENERGY SUPPRESSION

Within the NASA SBIR award PMCC developed and tested the 1st prototype of a spur energy suppressing 6-bit 20GS/s ADC for application in radio telescopes. Within the proposed project, the ADC TRL will be advanced further – the chip will be redesigned, fabricated, tested, and a versatile digitizer system will be built based on the developed part. Based on the initial assessment of AF requirements, the proposed ADC device is intended to achieve 4.5bit ENOB, 12GHz input bandwidth at up to 24GS/s rate and 40dB SFDR. In order to combine a low power consumption with high values of SINAD and SFDR, the ADC employs a novel calibration and sub-ADC parameter miss-match randomizing techniques which permit minimizing the energy of the spurs and increasing linearity. By the end of the Phase I project, PMCC will demonstrate the feasibility of the proposed project and will identify an end used from the AF. By the end of the Phase II project, PMCC will provide the AF and commercial customers with the ADC chips, packaged and tested devices, IP blocks and digitizer subsystems.