SBIR/STTR Research Award
Bootstrap Verification of FPGA Device Trust and Integrity
Award amount
$995,782Program and phase
SBIR · Phase IIAward year
2020Award details
- Awarding agency
- Department of Defense
- Branch
- Air Force
- Recipient company
- GRAF RESEARCH CORPORATION
- Proposal award date
- 2020-01-27
- Contract end date
- 2022-01-27
- UEI
- XHMHKK9DXVF6
- Solicitation number
- 18.2
- Topic code
- AF182-046
Research abstract
The software-based verification techniques proposed here improve on the state of the art by providing an inexpensive means of screening device integrity at any point from manufacture through use. This capability allows for protection against the load of sensitive IP onto untrusted devices without a requirement to maintain individual FPGA keys and part-specific boot material. Our approach is two-phase, with the run-time result of device verification linked to the bitstream load that puts end-user IP on the device.
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Dynamic Scheduler for Heterogeneous Multi-Tasking
- Measures and Methods for Optimal ELINT Signal Detection and Classification
- A Data-Centric Understanding of Satellite Maneuver Anomaly Classification within Space Domain Awareness
- Synthetic Data Generation for Enforte Attest
- Digital Erasure of Sensitive FPGA Systems
Research funding history
23 SBIR/STTR records share this UEI (2016–2026). Reported award amounts total $12,346,784. Reported amounts are not federal obligations.
Phases: Phase I, Phase II, Phase II – Direct to Phase II
Agencies: Department of Defense