Side Channel Attack Testbench Emulator (SCATE)

Team ECI will develop and demonstrate the CAD4EM solution to the SCATE problem: a feasible design for a software framework capable of measuring the vulnerability of RTL and Gate-level designs to side-channel attacks, and reporting the results using DARPA-approved metrics. To demonstrate the feasibility of the proposed software framework, Team ECI will develop three representative hardware implementations and evaluate all three for information leakage. The practicality of the proposed leakage evaluation framework will be validated with actual measurements from benchmarks configured into FPGAs and tested against actual side-channel attacks. Proof-of-concept experiments will be carried out to demonstrate the effectiveness of the security design rules countering EM side-channel attacks. The outcome of this feasibility work will be a design concept for a software framework capable of validating hardware designs in the early stages of development. This Phase I work will be used as the basis for a Phase II design that will be a potentially commercially marketable product attractive to electronic designers due to its capability of delivering significant cost savings. At the conclusion of the technical effort, Team ECI will demonstrate the CAD4EM solution in its current stage of development to DARPA and other interested government agencies or commercial companies.