Front End of Line and Back End of Line Layer Fabrication Partitioning for the Purpose of Design Intellectual Property (IP) Protection

A single IC manufacturer may use their detailed knowledge of a DoD ASIC IP to the detriment of the United States’ national interests. DoD program offices are not allowed to make use of the vast majority of manufacturing organizations worldwide, and are limited to a small number of DoD accredited “Trusted Suppliers”. This requirement generally drives up manufacturing costs, in that, ITAR compliant “Trusted Foundries”, use that compliance as an opportunity for greater profits. To combat the identified IP leakage and cost issues, a DMEA patent describes a methodology by which, a design is partitioned into multiple design layer files. Each layer file is bumped and sent to a different foundry for the fabrication of the one or more layers defined by that layer file. The multiple bumped metal layers are then bump assembled, thus creating a die stack whose functionality is identical to the original design file.  This Phase I effort will define and develop and conduct a feasibility study regarding the performance impacts of bumped die stacking chip IC metal layers and develop a plan for implementing the planned manufacturing and die stacking. These factors are presented and elaborated in the Phase I Technical Volume of this proposal.