Front End of Line and Back End of Line Layer Fabrication Partitioning for the Purpose of Design Intellectual Property (IP) Protection

To meet the demands of the DMEA182-002 SBIR solicitation (“Front End of Line and Back End of Line Layer Fabrication Partitioning for the Purpose of Design Intellectual Property Protection”), the MaXentric and UCLA team proposes the HIGHFIVE (Heterogeneous Integration Guideline Highlighting Fabrication of Information Veiled Electronics), which provides a practical verification flow using the circuit-based model verification procedure. The team will trade-study multiple chip-to-chip bonding process technologies, where one of candidates is UCLA’s Simple Universal Parallel intERface for CHIPS (SuperCHIPS) technology with the world finest pad pitch using the thermal compression bonding process. Carefully selected figure-of-merit (FOM) circuits will be used to evaluate impact to the electrical performance when the manufacturing obfuscation technique is applied. During Phase I work, the UCLA and MaXentric will characterize the interconnect between the front-end-of-line (active elements) and back-end-of-line (passive elements) layers, and simulate the performance of the FOM circuits for digital logic and analogy RF ASIC applications, respectively. Toward Phase II proposal, the team will make a plan for fabrication and test of the FOM circuits.