SBIR/STTR Research Award

Development of Novel RAD-Hard ASICs and a Modular Design Methodology Using Asynchronous Architectures

Award identifier 62429ba030ec7c2b5b70d7495dd4b7217fffd5a090ab718f4d668b92b0be20eeAwarding agency Department of Defense · Missile Defense Agency

Award amount

$100,000

Program and phase

SBIR · Phase I

Award year

2018

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Award details

Awarding agency
Department of Defense
Branch
Missile Defense Agency
Recipient company
NANOMATRONIX
Proposal award date
2018-06-25
Contract end date
2018-12-24
UEI
WAATQU93FVD1
Solicitation number
2018.1
Topic code
MDA18-007

Research abstract

The NMT/UA team propose to develop a radiation-hardened, low power, and highly robust delay-insensitive asynchronous circuit design methodology in 90nm technology, prototyped by designing a SET/SEL/SEU immune asynchronous microcontroller test chip (PIC 16C57, for example).The proposed Phase 1 SBIR effort will focus on design, simulation, prototyping and demonstration of the key functional blocks of the PIC 16C57 microcontroller* utilizing the Radiation-Hardened NULL Conventional Logic (RHNCL) architecture.Approved for Public Release | 18-MDA-9710 (6 Jul 18)

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

20 SBIR/STTR records share this UEI (2012–2025). Reported award amounts total $4,986,547. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, National Science Foundation, Department of Energy

Agency intelligence

Department of Defense

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