Irrefutable Tamper Logging through FPGA Key Management
Award amount
$997,499Program and phase
SBIR · Phase IIAward year
2017Award details
- Awarding agency
- Department of Defense
- Branch
- Missile Defense Agency
- Recipient company
- GRAF RESEARCH CORPORATION
- Proposal award date
- 2017-09-07
- Contract end date
- 2019-09-06
- UEI
- XHMHKK9DXVF6
- Solicitation number
- 2015.3
- Topic code
- MDA15-009
Research abstract
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Dynamic Scheduler for Heterogeneous Multi-Tasking
- Measures and Methods for Optimal ELINT Signal Detection and Classification
- A Data-Centric Understanding of Satellite Maneuver Anomaly Classification within Space Domain Awareness
- Synthetic Data Generation for Enforte Attest
- Digital Erasure of Sensitive FPGA Systems
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- Secure Protocol Unalterable Data (SPUD) Phase II
- Secure Protocol Unalterable Data (SPUD)
- Irrefutable Tamper Logging
- Irrefutable Tamper Evidence
- Irrefutable Tamper Evidence
Research funding history
23 SBIR/STTR records share this UEI (2016–2026). Reported award amounts total $12,346,784. Reported amounts are not federal obligations.
Phases: Phase I, Phase II, Phase II – Direct to Phase II
Agencies: Department of Defense