SBIR/STTR Research Award

Correlation Radiometer ASIC

Award identifier 53deac608e30ce166f9bb6df28aa1ab3ef11f922fe1baa0df578b9e23a7b31f5Awarding agency National Aeronautics and Space Administration

Award amount

$125,000

Program and phase

SBIR · Phase I

Award year

2017

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
PACIFIC MICROCHIP CORP.
Proposal award date
2017-06-09
Contract end date
2017-12-08
UEI
HRMGH9U56EQ1
Solicitation number
Not reported
Topic code
S1.03

Research abstract

The proposed project aims to develop an application specific integrated circuit (ASIC) for the NASA's microwave correlation radiometers required for space and airborne Earth sensing applications. The radiometer instrumentation installed on CubeSats and SmallSats is required to have small volume, low weight and consume low power. Currently used correlating radiometers rely on analog signal processing, thus are bulky, power hungry and cannot be reprogrammed. Analog filter parameters tend to be unstable over temperature, power supply voltage, may degrade over time and need tuning. The proposed low-power, rad-hard ASIC will operate with microwave correlation radiometer front ends down-converting the RF to up to 10GHz IF quadrature signals. The ASIC will include digitizers, bandpass filters, cross-correlators, totalizers, serializers, an output data interface and an I2C interface for the ASIC's programming. Bandpass filters will split up the digitized quadrature IF input signals into bands (up to 16), will cross-correlate the signals within each band and will ship out the resultant data in a convenient format. Instead of analog signal processing performing a strictly defined function, the ASIC will employ a digital signal processing which can be reprogrammed to adopt specific parameters of the filter block such as the number of bands, each filter's corner frequency, bandwidth and filter's order. A number of innovations will be introduced to the ASIC in order to combine programmability, low power consumption and radiation tolerance. The project's Phase I will provide the proof of feasibility of implementing the proposed ASIC. Phase II will include finishing the design, chip fabrication, testing and delivering the ADC prototypes which will be ready for commercialization in Phase III.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

49 SBIR/STTR records share this UEI (2010–2025). Reported award amounts total $21,447,669. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: National Aeronautics and Space Administration, Department of Energy, Department of Defense, National Science Foundation

Agency intelligence

National Aeronautics and Space Administration

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