SBIR/STTR Research Award

Low-Power Radiation Tolerant 4GHz Bandwidth 16k Channel Spectrometer ASIC

Award identifier aa9817265424a70f934688152ed6e3d1c4d0113ace61d949d6875a236b1c5f1cAwarding agency National Aeronautics and Space Administration

Award amount

$125,000

Program and phase

SBIR · Phase I

Award year

2017

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
PACIFIC MICROCHIP CORP.
Proposal award date
2017-06-09
Contract end date
2017-12-08
UEI
HRMGH9U56EQ1
Solicitation number
Not reported
Topic code
S1.03

Research abstract

Spectrometers currently employed or under development by NASA are based on a printed circuit board (PCB) including field programmable arrays (FPGAs) and a number of other discrete components. An application specific integrated circuit (ASIC) based spectrometer offers a great reduction in weight, volume and power consumption compared to the FPGA/PCB based implementation. This proposal aims to develop a radiation-hardened (RH) low-power (LP) poly-phase spectrometer (PPS) ASIC. The proposed RH LP PPS ASIC aims to achieve a 4GHz bandwidth and 214 (16384) frequency bins. In order to implement the required functionality and meet the specifications while consuming below 2.5W of power, the proposed ASIC will include a state-of-the-art ADC, a demultiplexer, a poly-phase filter bank, a windowing function, a fast-Fourier-transform core, a fast-Fourier-data analysis block, a data readout, a digital control unit and testing features. Tolerance to at least 4Mrads of total ionizing dose (TID) radiation and immunity to the single event effects (SEEs) will be achieved by employing radiation hardening by design, by layout, and by system techniques and also by applying an ultra-thin gate oxide technology for implementation. Low power consumption will be achieved by employing special multiplier-less-accumulators and multiplier-less-"butterflies". The power consumption will be further reduced by switching off the unused ASIC's blocks, down rating the clock frequency, eliminating unnecessary buffering and applying the 28nm CMOS technology. Phase I work will provide the proof of feasibility of implementing the proposed spectrometer ASIC. Phase II will result in the silicon proven ASIC's prototypes ready for commercialization in Phase III.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

49 SBIR/STTR records share this UEI (2010–2025). Reported award amounts total $21,447,669. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: National Aeronautics and Space Administration, Department of Energy, Department of Defense, National Science Foundation

Agency intelligence

National Aeronautics and Space Administration

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