Digital Readout Integrated Circuits With Efficient, Low Power On-chip Data Compression

There is a continuing push for very large format, very high dynamic range, very fast frame rate digital Infrared Focal Plane Arrays (IRFPAs) by the DOD community. Some emerging applications require FPA data rates >100 Gb/s; for commonly used Low Voltage Differential Signal (LVDS) output circuits with 1 Gb/s capability, this translates to 100 pairs of Dewar feedthrough wires creating un-manageable power and thermal dissipation. Efficient on-FPA data compression techniques are required to reduce FPA output data rates. On Phase I Black Forest Engineering (BFE) will design a 1k x 1k Digital Readout Integrated Circuit (DROIC) in a 10 m pixel pitch with 18-bit ADC and lossless compression to support the equivalent of 100 Gb/s FPA data rates with <25 pairs of Dewar digital output wires and usingslightly lossy compression <10 pairs of output wires. FPA architectures will also be investigated to provide additional temporal compression capability by adding ASIC/memory beneath the FPA ROIC for additional video compression. On Phase I, BFE will simulate compression capability using IR images. A Phase II development will provide a path to a Phase II ROIC/FPA demonstration.