Digital Readout Integrated Circuits With Efficient, Low Power On-chip Data Compression Development

This proposal outlines an on-chip data compression scheme for large format digital pixel readout integrated circuits (DPROICs) to achieve high frame-rates using standard high speed interfaces like Low Voltage Differential Signaling (LVDS). Using a combination of lossless compression and high quality lossy compression, the proposed compressing scheme with enable high quality infrared imaging without requiring high data bandwidths, thereby requiring fewer LVDS ports and in turn reducing power consumption and thermal dissipation. The compression scheme can be readily used in conventional DROICs as well, thereby expanding its application spectrum to most Army and DoD applications. The proposed DPROIC with on-chip data compression will be a complete camera-on-chip architecture when combined with infrared detectors. The DPROIC will be implemented in a mature CMOS process with much more reasonable mask costs as compared to that of state-of-the-art line width processes, saving the government money and broadening the possible supplier base.