SBIR/STTR Research Award
Automatically Generating Reconfigurable Memory & Central Processing Unit (CPU) Architectures
Award amount
$125,000Program and phase
SBIR · Phase IAward year
2015Award details
- Awarding agency
- Department of Defense
- Branch
- Missile Defense Agency
- Recipient company
- BLUERISC INC
- Proposal award date
- 2014-12-22
- Contract end date
- 2015-07-21
- UEI
- LVWLKDJURJL1
- Solicitation number
- 2014.2
- Topic code
- MDA14-006
Research abstract
The proposed solution automatically co-creates a per-device-unique, reconfigurable processor, as well as associated enabling software build environment, enabling unique execution environments, instruction set, and memory interfaces. The unique execution environments and memory interfaces provide foundational resilience and heightened levels of protection. Approved for Public Release 14-MDA-8047 (14 Nov 14)
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Large Language Models for System Security Engineering Analysis
- Navigation Warfare Situational Awareness with AI/ML
- Asymmetric LLM-aided Cyber Effects
- Navigation Warfare Situational Awareness with AI/ML
- Novel Processor Architectures for Probabilistic Computing in Survivability Controllers
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- UniQore Secure Soft-core Processor
- Reconfigurable Memory or Central Processing Unit (CPU) Instruction Architecture
- Reconfigurable Memory or Central Processing Unit (CPU) Instruction Architecture
- Lightweight Approach to System Protection
Research funding history
60 SBIR/STTR records share this UEI (2003–2025). Reported award amounts total $29,565,062. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense, Department of Homeland Security, National Science Foundation, Department of Energy