SBIR/STTR Research Award
Reconfigurable Memory or Central Processing Unit (CPU) Instruction Architecture
Award amount
$124,422Program and phase
SBIR · Phase IAward year
2015Award details
- Awarding agency
- Department of Defense
- Branch
- Missile Defense Agency
- Recipient company
- Lewis Innovative Technologies, Inc.
- Proposal award date
- 2014-12-22
- Contract end date
- 2015-07-21
- UEI
- CV3PNJV2VVX3
- Solicitation number
- 2014.2
- Topic code
- MDA14-006
Research abstract
Lewis Innovative Technologies, Inc. (LIT) proposes a reconfigurable memory addressing architecture that provides both hardware and software protection. The LIT system obfuscates (modifies) the memory address of critical data interface with a data/software binding technique. Approved for Public Release 14-MDA-8047 (14 Nov 14)
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Physical Uncloneable Function (PUF) Encryption Key
- Anti-Tamper Technology for Missile Defense
- Anti-Reverse Engineering (RE) Techniques
- Field Programmable Gate Array (FPGA) Physical Unclonable Functions
- Anti-Tamper Technology for Missile Defense
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- UniQore Secure Soft-core Processor
- Reconfigurable Memory or Central Processing Unit (CPU) Instruction Architecture
- Automatically Generating Reconfigurable Memory & Central Processing Unit (CPU) Architectures
- Lightweight Approach to System Protection
Research funding history
27 SBIR/STTR records share this UEI (2001–2015). Reported award amounts total $10,693,020. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense