Fully Scalable Power-Efficient Electronic Digitizer Architecture

During Phase I of this SBIR program, Photonic Systems, Inc. (PSI) and Systems Technology & Research (STR) developed a design for an ultra-wideband, power-efficient, high-performance analog-to-digital converter (ADC) using a novel combination of electronic and photonic hardware together with digital processing software. During Phase II, we will develop a prototype with a sample rate of >10 GS/s and >8 effective bits (ENOB) at 20 GHz, which can be operated either in the classic Nyquist sampling mode or in a compressive sensing mode. The photonic ADC design developed in phase I can easily be adapted to the design of other ADCs at different points in the ENOB vs. sampling rate trade space. The PSI/STR teams innovative design meets this programs challenging ENOB, dc power, and sampling rate goals by leveraging the team members work on previous ADC programs: photonic sampling, multi-channel ADC interleaving, and signal processing algorithms for calibration, nonlinearity correction, and compressive sensing. The prototype ADC uses all-COTS parts, thereby achieving extraordinary performance using ordinary components. The approach is scalable in ENOB and sample rate as the performance of electronic ADCs improves, and its output is compatible with standard interfaces for digital data signal transfer.