Signal Processing with Memristive Devices

ABSTRACT: The team of MicroXact, Inc., UCSB and UC Irvine proposes to develop a CMOS-compatible memristor, which will enable next generation signal processors, extremely efficient (i.e. dense, inexpensive, low power consuming), with the capabilities for massively parallel signal processing. More specifically, we offer to solve the reliability and repeatability problem in memristive devices by utilizing new design and fabrication processes. Specifically to the Air Force, the proposed solution can provide integrated processing platforms for Unmanned Aerial Vehicles (UAVs) and other devices, where the processing speed and parallelism are critical. Proposed memristive devices will allow the development of an faster and more capable DSP and FPGAs for tomorrow"s high speed signal processing, and the development of reliable and repeatable memristive devices will have innumerable potential applications. In Phase I the team developed a first model of the resistive switching in metal-oxide metal memristors and conceived the fabrication process that would provide reliable and repeatable memristor devices. In Phase II the team will improve and experimentally verify the developed model, will optimize fabrication processes and will demonstrated reliable and repeatable fabrication of memristors. In Phase III MicroXact will commercialize the proposed technology. BENEFIT: According to the ITRS 2007 Roadmap, currently used CMOS technologies will reach the 18-nm technology node and 7-nm physical gate length by 2018. It is anticipated that beyond this point, CMOS scaling will likely become very difficult if not impossible due to power dissipation problem. This represents a tremendous business opportunity for new technologies that will be able to solve the power dissipation problem to capture significant portion of the humongous ($200 billions) market in ten years from now. The team of MicroXact Inc. and UCSB proposes to develop this revolutionary memristive devices and circuits which have the potential to significantly increased efficiency and reduced power consumption by achieving highly parallel information architectures with low heat dissipation. CMOS compatibility of the proposed solution permits significant extending of the lifetime of fabrication facilities and equipment, thus providing the tremendous savings on otherwise imminent replacements of the currently employed technology.