Signal Processing with Memristive Devices

To streamline data processing in, e.g., hyperspectral imaging, new massively parallel data processing circuits are needed. The team of MicroXact Inc. and UC Santa Barbara propose to develop circuits based on completely novel computing paradigm, which could be extremely efficient (i.e. dense, relatively inexpensive, and consume very little power) for massively parallel signal processing. We offer to (1) develop fully CMOS compatible hybrid circuits based on the conventional CMOS technology and recently suggested thin film memristive devices; (2) demonstrate analog dot-product computation, which is a core operation for all signal processing applications; and (3) perform rigorous and impartial comparison of their performance to that of flash based circuits. In phase I we will design CMOS compatible memristive devices, experimentally demonstrate the memristive behavior of fabricated devices and theoretically analyze analog and mixed signal memristor circuits. In Phase II we will optimize single memristive devices, develop fully CMOS compatible prototype of hybrid circuits, and will fabricate, test and characterize the memristor circuit designed for dot product operation. We will further develop large scale hybrid architectures for signal processing and bio-inspired networks and perform their detailed simulations using models derived from experimental data. In Phase III we will commercialize the developed technology BENEFIT: According to the ITRS 2007 Roadmap, currently used CMOS technologies will reach the 18-nm technology node and 7-nm physical gate length by 2018. It is anticipated that beyond this point, CMOS scaling will likely become very difficult if not impossible due to power dissipation problem. This represents a tremendous business opportunity for new technologies that will be able to solve the power dissipation problem to capture significant portion of the humongous ($200 billions) market in ten years from now. The team of MicroXact Inc. and UCSB proposes to develop this revolutionary memristive devices and circuits which has the potential to significantly increased efficiency and reduced power consumption by achieving highly parallel information architectures with low heat dissipation. CMOS compatibility of the proposed solution permits significant extending of the lifetime of fabrication facilities and equipment, thus providing the tremendous savings on otherwise imminent replacements of the currently employed technology