Solutions for Single-Event Effects in Ultra Deep Submicron Semiconductor Technologies Using Simulation and Layout Techniques

This project offers two powerful and efficient solutions to solve the mounting problems in design of radiation hard electronics: a range of ultra hard, high performance, sequential and combinatorial logic blocks based on the new, and enormously effective, LEAP RHBD layout methodology, and an accurate and efficient analysis, design, and simulation solution for single events. The Layout design through Error Aware Positioning (LEAP) technique can reduce single event error rates by several orders of magnitude through rearrangements of the layout alone. The technique incurs minimal performance penalties. It requires no changes in the manufacturing process, and can therefore be applied for manufacturing in any standard semiconductor technology, which ensures cost effective manufacturing. The tremendous error rate reductions achievable by this technique have been verified experimentally in 180nm technology and in 28nm technology. The single event analysis and design software developed in this project is created by bringing together the advanced single event analysis tools from ISDE and RCI. This modeling solution allows for an accurate and predictive analysis of the effects of layout changes on single event behavior, something which is just not possible with other single event simulation techniques.