High-Speed ADC SoC with Ultra-Wide Input Dynamic Range

Integration of analog data preprocessing and digitization within a single integrated circuit or multi-chip module would significantly improve the performance and reliability of DOE experimental systems while reducing their power consumption, complexity, and cost. Processing of wide dynamic range signals ( & gt16 bits) with high accuracy ( & gt7 bits) and sampling rates above 2.0GS/s is vital for NEP experiments scheduled for the year of 2011 and beyond. Thus, the development of a single-chip, power-efficient ADC with a wide input dynamic range, high sampling rate, and FPGA-compatible output interface is important for the upgrade of existing and the development of novel advanced experimental systems. To address the described requirements, our company in cooperation with Oak Ridge National Laboratory proposes to develop and fabricate a multi-channel, power-efficient ( & lt;1.0W/GSample) ADC system-on-chip with a dynamic range up to 17 bits and a sampling rate up to 2.5GS/s that incorporates a broadband analog 1-to-3 data splitter with different attenuation coefficients followed by three 7-bit ADCs, one-out-of-3 selector, and an output LVDS interface. The chip will deliver 630 Mb/s parallel data streams with a selectable 9-bit or 16-bit width, which can be processed by standard Vertex 5 FPGA from Xilinx. The technical benefits of the new ADC will include an ultra-wide input dynamic range, high operational speed, low power consumption, and FPGA-compatible output interface. All these features are vital for the success of different scientific experiments in Nuclear and High-Energy Physics. The developed technology will be also beneficial for military and commercial data acquisition systems, satellite communications, medical image processing, etc.