SBIR/STTR Research Award

Design and Fabrication Techniques for 3-Dimensional Integrated Circuits

Award identifier 9d3e13a4738f8403a59f5239d1b9cb8f85038311ec50a0811427da4706f14e4aAwarding agency Department of Defense · Defense Advanced Research Projects Agency

Award amount

$750,000

Program and phase

SBIR · Phase II

Award year

2010

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Award details

Awarding agency
Department of Defense
Branch
Defense Advanced Research Projects Agency
Recipient company
GOOFYFOOT LABS LLC
Proposal award date
2010-08-30
Contract end date
2012-08-29
UEI
MTPCSNM9NV96
Solicitation number
2009.1
Topic code
SB091-008

Research abstract

The 3-D integration of systems through monolithic wafer stacking is an emerging technology that can alleviate power, delay, and area problems for digital circuits and can enable a host of new applications in the system on a chip design space. Currently, CAD tools for 3-D integration are severely lacking stagnating potentially explosive growth of the technology. GoofyFoot Labs proposes TESI3d, a CAD tool to efficiently and accurately explore the complex 3-D design space. We will develop a full-scale prototype, which will then be used to design and evaluate 3-D systems.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

6 SBIR/STTR records share this UEI (2009–2022). Reported award amounts total $2,222,927. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration

Agency intelligence

Department of Defense

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