Design and Fabrication Techniques for 3-Dimensional Integrated Circuits
Award amount
$750,000Program and phase
SBIR · Phase IIAward year
2010Award details
- Awarding agency
- Department of Defense
- Branch
- Defense Advanced Research Projects Agency
- Recipient company
- GOOFYFOOT LABS LLC
- Proposal award date
- 2010-08-30
- Contract end date
- 2012-08-29
- UEI
- MTPCSNM9NV96
- Solicitation number
- 2009.1
- Topic code
- SB091-008
Research abstract
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- EdgeNF CPU - 28-nm, rad hard, 1.7-GHz CPU
- Extreme Environment, Rad Hard, High Performance, Low Power FPGA for Space Applications
- High Performance/Throughput, Low Latency and Low Power Field Programmable Gate Array (FPGA) for Software Defined Radio (SDR) and Cognitive Radio (CR)
- High Performance/Throughput, Low Latency and Low Power Field Programmable Gate Array (FPGA) for Software Defined Radio (SDR) and Cognitive Radio (CR)
- Design and Fabrication Techniques for 3-Dimensional Integrated Circuits
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- CAD Tool Development and Design for 3D Integrated Circuits: Optimizing Thermal Effects, Delay, Placement and Routing
- Design and Fabrication Techniques for 3-Dimensional Integrated Circuits
Research funding history
6 SBIR/STTR records share this UEI (2009–2022). Reported award amounts total $2,222,927. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense, National Aeronautics and Space Administration