Design and Fabrication Techniques for 3-Dimensional Integrated Circuits

The 3-D integration of systems through monolithic wafer stacking is an emerging technology that can alleviate power, delay, and area problems for digital circuits and can enable a host of new applications in the System-on-Chip design space. Currently, CAD tools for 3-D integration are severely lacking stagnating potentially explosive growth of the technology. GoofyFoot Labs will develop a CAD verification suite to accurately and efficiently simulate 3-D ICs for issues that are of chief concern to 3-D designers: thermal, signal integrity, and reliability. Existing commercial 3-D CAD tools are limited to place and route and layout. No commercial tool exists to perform full-scale verification incorporating 3-D thermal and signal integrity effects. Designers can use the proposed CAD tool at all stages of the design cycle to determine the performance and reliability effects induced by wafer stacking. During Phase I, we will develop the tool framework and algorithms and demonstrate performance improvements achievable with the new framework. During Phase II, we will develop a full-scale prototype, which will then be used to design and evaluate and an ultra low power, 3-D integrated sensor.