Design and Fabrication Techniques for 3-Dimensional Integrated Circuits
Award amount
$98,955Program and phase
SBIR · Phase IAward year
2009Award details
- Awarding agency
- Department of Defense
- Branch
- Defense Advanced Research Projects Agency
- Recipient company
- NHANCED SEMICONDUCTORS, INC.
- Proposal award date
- 2009-12-29
- Contract end date
- 2010-08-30
- UEI
- LATHGF1NRTC1
- Solicitation number
- 2009.1
- Topic code
- SB091-008
Research abstract
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- CMOS Integrated With Float Zone Pixel Sensor
- Micro-Transfer-Printing Of Repeaters On Passive Interposer
- Energy-Efficient Reconfigurable Universal Accelerator Interconnect
- CMOS Integrated With Float Zone Pixel Sensor
- A New Cost-Effective Engineered Substrate
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- Design and Fabrication Techniques for 3-Dimensional Integrated Circuits
- CAD Tool Development and Design for 3D Integrated Circuits: Optimizing Thermal Effects, Delay, Placement and Routing
- Design and Fabrication Techniques for 3-Dimensional Integrated Circuits
Research funding history
21 SBIR/STTR records share this UEI (2008–2021). Reported award amounts total $9,451,098. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense, Department of Energy, National Aeronautics and Space Administration