SBIR/STTR Research Award

Design and Fabrication Techniques for 3-Dimensional Integrated Circuits

Award identifier d7dce3a1447fcf29d1f7b588c451f332b8abdec81472da13834ea70e3e7c589dAwarding agency Department of Defense · Defense Advanced Research Projects Agency

Award amount

$98,955

Program and phase

SBIR · Phase I

Award year

2009

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Award details

Awarding agency
Department of Defense
Branch
Defense Advanced Research Projects Agency
Recipient company
NHANCED SEMICONDUCTORS, INC.
Proposal award date
2009-12-29
Contract end date
2010-08-30
UEI
LATHGF1NRTC1
Solicitation number
2009.1
Topic code
SB091-008

Research abstract

Tezzaron proposes to use and extend its 3D wafer stacking technology to produce a 8Gb DRAM. The device will be made from 8 layers of memory and a single logic control layer, providing density far beyond the capability of current commercial technology. A device of this density can offer significant improvements in system power, size, weight and performance. The major unknown in creating a device like this, are the issues that may arise when 3D integration is practiced beyond Tezzaron current devices of 3 or 4 tiers. In Phase I "dummy" wafers will be stacked to determine the feasibility of the planned 9 layer device to be fabricated as part of Phase II.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

21 SBIR/STTR records share this UEI (2008–2021). Reported award amounts total $9,451,098. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, Department of Energy, National Aeronautics and Space Administration

Agency intelligence

Department of Defense

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